1. Field of the Invention
The present invention relates to an operational amplifier used in portable devices, such as mobile phones, digital cameras, and so on, and more specifically, to an operational amplifier capable of operating at low voltage.
2. Description of the Related Art
Recently, there is increasing demand for portable devices, such as mobile phones, digital cameras, and so on that are capable of low-voltage operation with low power consumption. For such devices, it is extremely important to have a high-performance operational amplifier capable of operating under such low-power voltage conditions. Such an operational amplifier may be formed of a rail-to-rail-input folded-cascade-type AB-class operational amplifier to achieve stable operation under low-power voltage conditions.
FIG. 1 is a circuit diagram of a rail-to-rail-input folded-cascade-type AB-class operational amplifier 100. The operational amplifier 100 includes a PMOS (P-type Metal Oxide Semiconductor) transistor input unit 101, an NMOS (N-type Metal Oxide Semiconductor) transistor input unit 102, a PMOS transistor cascade amplifier unit 103, an NMOS transistor cascade amplifier unit 104, and an output unit 105.
The PMOS transistor input unit 101 includes a bias current MOS transistor M101 and a pair of PMOS transistors M102 and M103. The PMOS transistors M102 and M103 form a differential pair. A predetermined bias voltage bias1 is input to a gate of the bias current MOS transistor M101 so that a current source is formed.
The NMOS transistor input unit 102 includes a bias current MOS transistor M104 and a pair of NMOS transistors M105 and M106. The NMOS transistors M105 and M106 form a differential pair. A predetermined bias voltage bias2 is input to a gate of the bias current MOS transistor M104 so that a current source is formed.
The PMOS transistor cascade amplifier unit 103 includes load current source MOS transistors M107 and M108, and gate-grounded MOS (ggMOS) transistors M109 and M110. A predetermined bias voltage bias3 is input to the gate of each of the load current source MOS transistors M107 and M108 so that current sources are formed. Further, a predetermined bias voltage bias4 is input to the gate of each of the ggMOS transistors M109 and M110 so that the load current source MOS transistors M107 and M108 operate in each saturation region.
The NMOS transistor cascade amplifier unit 104 includes load current source MOS transistors M115 and M116, and gate-grounded MOS (ggMOS) transistors M113 and M114. A predetermined bias voltage bias7 is input to the gate of each of the ggMOS transistors M113 and M114 so that the load current source MOS transistors M115 and M116 operate in each saturation region.
The output unit 105 includes an NMOS transistor N111 and a PMOS transistor M112 in an input stage, and further includes a PMOS transistor M117 and an NMOS transistor N118 in an output stage.
The operational amplifier 100 operates as an AB-class operational amplifier by inputting a predetermined bias voltage bias5 to a gate of the NMOS transistor N111 and a predetermined bias voltage bias6 to a gate of the PMOS transistor N112. In the AB-class operational amplifier, the PMOS transistor M117 and the NMOS transistor N118 each operate in a stable state.
To reduce output noise, transistors which may contribute noise generation are formed of low-voltage transistors, each of which has high transconductance gm. In FIG. 1, the PMOS transistors M102, M103, M107 and M108 and the NMOS transistors M105, M106, M115 and M116 are formed of low-voltage transistors.
FIG. 2 is a circuit diagram of the operational amplifier 100 when such transistors in FIG. 1 are replaced by low-voltage transistors. In FIG. 2, NMOS transistors M119 and M120, and PMOS transistors M102 are employed to protect the low-voltage transistors under normal operating conditions.
FIG. 3 is an equivalent circuit diagram of the operational amplifier 100 when such AB-class operational amplifier operates in a sleep mode. As shown in FIG. 3, in sleep mode, each gate of the PMOS transistors M101, M107, M108, M110 and M117 is connected to power supply voltage VDD, and each gate of the NMOS transistors M104, M113, M114, and M118 is connected to ground voltage GND. Under these conditions, each node of sources of the PMOS transistors M102 and M103, drains of the NMOS transistors M105 and M106, and a drain of the PMOS M107 attains a high impedance. Accordingly, a high voltage may be applied to these nodes. When the high voltage exceeds a maximum breakdown voltage of each MOS transistor, failure such as destruction of the MOS transistors may occur.